1. Field
The present invention relates to electronic circuits and, more particularly, to a clock and data recovery circuit with high jitter tolerance and fast phase locking
2. Background
The use of high-speed serial communication links in electronic systems continues to increase. High-speed serial communication links can operate according to various standards such as Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Serial Advanced Technology Attachment (SATA), and Peripheral Component Interconnect Express (PCIe) interfaces. A clock and data recovery circuit (CDR) is used to recover data from a serial communication link and recover a clock that signals the timing of the data.
In some systems, for example, USB, the serial data can have large instantaneous timing jitter. Prior CDRs can produce errors (e.g., the recovered data is incorrect) in some jitter conditions. Prior CDRs can also exhibit slow initial locking to the input data. Some prior CDRs have included complex circuitry in an attempt to handle the timing jitter.